Comparative study and prediction modeling of photonic ring Network on Chip architectures

Abstract

Multicore systems are becoming state-of-the-art and therefore need fast and energy efficient interconnects to take full advantage of the computational capabilities. Integration of silicon photonics with traditional electrical interconnect in Network on Chip (NoC) proposes a promising solution for overcoming the scalability issues of electrical interconnect. In this paper, we implement the simulation model for two Optical NoC architectures and compare their performance. We also derive and evaluate a prediction modeling technique for the design space exploration of ONoCs. Our proposed model accurately predicts packet latency, static and dynamic energy consumption of the network. This work specifically addresses the challenge of accurately estimating performance metrics without having to incur high costs of exhaustive simulations. Our case study shows that by using only 10% of the entire design space, our proposed technique builds a prediction model that achieved average error rates as low as 5.44%, 2.67% and 3.24% for network packet latency, static and dynamic energy consumption respectively in six different benchmarks from Splash-2 benchmark suite.