Abstract
As the number of transistors in the chip has reached 2 billion, the power dissipation becomes the bottleneck in chip design, as power increases, the thermal dissipation also increases which in turn reduces the reliability of the chip and increases the packaging cost. Nowadays various power reduction techniques are adopted to target the power. Bus encoding technique is one among which reduces the dynamic power by reducing the switching activity in off chip wires. Various algorithms for bus encoding are proposed, this paper compares the different bus encoding scheme in terms of area, timing overhead and efficiency of power reduction and switching activity reduction.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.