Crosstalk and Power Reduction Using Bus Encoding in RC Coupled VLSI Interconnects

Abstract

For System on-chip (SoC) designs in current Deep Submicron (DSM) era, interconnects play important role in overall performance of the chip. The factors such as propagation delay, power dissipation and crosstalk through RC modeled interconnects substantially affects the entire working of the chip. Functional crosstalk and crosstalk induced propagation delay have recently emerged as major sources of faults. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition in previous state of wire as well as when transitions are in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. This paper proposes encoding schemes in order to achieve reduction in transitions between the previous and present states of wire as well as transitions in adjacent wires. The reduction in transition improves the performance in terms of power dissipation, coupling activity and delay in on-chip bus.