Comparative Analysis of Parameter Extractor for Low-Power Precomputation Based Content Addressable Memory

Abstract

Content Addressable Memory (CAM) is used in high speed searching applications and also in data compression. Recently in the network computing era, fast lookup tables are required for address resolution in network switches and routers such as LAN bridges/switches, ATM switches, and layer-3 switches. High search speed is obtained by parallel comparison. But power consumption is high in case of parallel comparison. In precomputation based CAM (PB-CAM) the comparison operation is divided into two stages to reduce the massive comparison operations in data searches. Precomputation is the way of comparing the extracted parameter from the input data in the first stage. The second stage comparison is done between the matched output of the first stage and the input data. In this paper, a Remainder Function parameter extractor is proposed as a precomputation technique to enhance the performance of low power PB-CAM. The experimental results obtained using 90 nm CMOS technology in the Cadence virtuoso show that the proposed approach achieves an average of 91% in power reduction.