Comparative Analysis of Logic Gates Based on Spin Transfer Torque (STT) and Differential Spin Hall Effect (DSHE) Switching Mechanisms

Abstract

Conventional complementary metal oxide semiconductor (CMOS) based memory and logic gates, has a major issue of large static power dissipation below 45-nm technology nodes. The most attractive property of CMOS technology was scalability. However, with continuous scaling short channel effects (SCEs) (like quantum mechanical tunneling, mobility degradation, hot carrier effects, drain induced barrier lowering) deteriorate the functionality of logic circuits. Hence, the researchers are looking for a possible substitute of conventional CMOS technology, as it is approaching towards its physical limit. The most promising substitute of the CMOS among the novel technologies is spintronics due to low power dissipation, non-volatility, high density, high endurance, and its easy integration with CMOS. There are two methods of switching: Spin Transfer Torque (STT) and Spin Hall Effect (SHE). This paper aims to analyze and compare the characteristics of hybrid CMOS/MTJ logic gates based on STT and Differential Spin Hall Effect (DSHE) magnetic random access memories (MRAMs). The logic gates based on STT-MRAM have certain limitations related to reliability and high write energy. The SPICE simulations using 45-nm standard CMOS design kit have been carried out to show that the power dissipation reduction is 95.6% in DSHE as compared to STT based logic gates. Moreover, write circuit for DSHE-MRAM consumes only 5.28 fJ energy per bit.