Comparative Analysis of Dual Metal Gate Fully Depleted SOI FET With/Without δ-Doped Insulated Layer for AF Application

Abstract

This paper presents and compares dual metal gate fully depleted SOI FET with/without δ-doped insulated layer for thermal efficacy, scalability and analog/RF performance. In the proposed device, a delta doped layer (DMG SOI FET-δ) is incorporated to boost its analog performance. Also, the proposed study analyzes the effect on transconductance, and voltage gain from several structural characteristics. The doped layer is seen to minimize the self-heating and enhance analog parameters such as trans-conductance, output conductance and transconductance generation factor over DMG SOI FET. Furthermore, the diminished short-channel impacts such as DIBL, subthreshold swing and parasitic capacitances make the scaling possible. The brief introduction of fabrication flow of DMG SOI FET-δ has been proposed. The comparison has been done between DMG SOI FET-δ and DMG SOI FET, to validate the advantages of the proposed structure for the realization of low power and high-frequency applications.