Compact SPICE Model of Topological Textures on Magnetic Racetracks for Design Space Exploration

Abstract

Magnetic Topological Textures (MTTs) have the potential to become the building block of future memory and logic-in-memory devices due to their compact size and non-volatility. However, these MTTs are used in conjunction with the CMOS control circuit to design memory and logic-in-memory devices. Micromagnetic and SPICE simulations need to be carried out separately for MTT and CMOS, respectively, to evaluate the performance of these hybrid devices. Thus, a SPICE model that can emulate the physical behavior of the MTT would allow the designers to evaluate the performance of these hybrid devices accurately and enable design space exploration. In this paper, we build a compact and modular SPICE model of MTT nucleation, motion, detection, and annihilation on the racetrack by extracting parameters from micromagnetic simulation tools. We also build a CMOS-MTT generic racetrack circuit model in SPICE and validate the model’s accuracy by comparing it with micromagnetic simulation results. As we can perform the simulations fully within SPICE while capturing the essential physics of the MTTs on the racetrack, we enable simulation runtime acceleration by a factor of > 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> and > 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> times approximately compared to the micromagnetic simulations carried out with MUMAX3 and OOMMF. We envision that the proposed model will enable design and application explorations and device-circuit co-simulation, co-design, and co-optimization for the emerging MTT-based computing systems.