Compact modeling and design optimization of carbon nanotube field-effect transistors for the sub-10-nm technology nodes

Abstract

Summary form only given. Single-wall semiconducting carbon nanotube (CNT) field-effect transistors (CNFETs) have been among the foremost candidates to complement Si and extend CMOS technology scaling to sub-10-nm technology thanks to the atomically thin body of CNTs and their near-ballistic transport [1-3]. However, non-idealities such as high contact resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) [4], parasitic capacitance and tunneling leakage current can diminish the superior intrinsic electrical properties of CNTs in a highly scaled CNFET. Here we present the first data-calibrated compact model for CNFETs which captures dimensional scaling effects, metal-CNT contact resistance, parasitic capacitance, and direct source-to-drain tunneling leakage current. We then use this model to study design trade-offs and identify the remaining critical challenges for the CNFET technology. The model has been implemented in Verilog-A, is now available online [5], and will be described here for the first time.