Communication Centric Floorplanning of NoC Based System on Chip

Abstract

In the past, shared bus based architecture was used as a communication architecture in SoC. They consume more area, power and do not meet the proper bandwidth requirement. Network on chip (NoC) is evolving as a viable communication architecture because they offer better scalability, modularity, design predictability, lower power consumption and shorter latency compared to bus based systems. Application Specific Network on chip (ASNoC) topologies are found to be superior than regular NoC topologies for designing SoC with known communication demands. In this paper, a communication centric floorplanning algorithm is proposed in which communication architecture is synthesized along with the floor plan. This is achieved by grouping IP cores based on their communication requirements in pre floorplanning stage and placing network components judiciously in the post floorplanning stage. Simulated annealing is used as a search engine to obtain the optimal location of IP cores and network components in the floorplan.