Design of reconfigurable and reliable application specific network on chip for R3TOS

Abstract

In this paper, design of a novel reliable Application Specific Network on Chip (ASNoC) with reconfigurability and its integration with Reliable Reconfigurable Real Time Operating System (R3TOS) is presented. Network on Chip (NoC) is a well known scalable communication paradigm to avoid the communication bottleneck in bus based communications. Reconfigurable Field Programmable Gate Arrays (FPGAs) are particularly suited for applications that can be broken into a number of different tasks. Reconfigurability of tasks at runtime enhances the system performance metrics. In earlier literatures, Operating System (OS) was used as the medium, for communication between different tasks at run time. This approach provided significant bottlenecks, as Operating System was using the low bandwidth Internal Configuration Access Port (ICAP) and Processor Configuration Access Port (PCAP) for communication between tasks and itself. In this paper, a novel NoC structure is used as the communication interface between different tasks. This approach releases the Operating System from managing the inter task communications. This will result in high bandwidth communication between different tasks. A novel architecture router for NoC which has been proposed removes the head of line blocking by using a dedicated head flit first in first out (FIFO) buffer and data flits being stored in different FIFOs for each input port with a control logic dedicated for this operation. It also removes the requirement for tail flit by introducing the number of data flits in the head flit itself. Also, in order to improve reliability level, we incorporate the novel partially reconfigurable Error Detection and Correction techniques in this NoC. This architecture is implemented in Zynq 7000 series.