Comments on “Improved designs of digit-by-digit decimal multiplier”

Abstract

Decimal multiplication is one of the complex operations in the applications that still radix-10 representations are preferred. To improve the performance, Ahmed et al. proposed some fast and area efficient binary-to-decimal converters to be used for both partial product generation and partial product reduction stages of digit-by-digit decimal multiplication. These converters that transform each binary result to binary coded decimal (BCD) representation utilize two new types of binary-to-decimal converter cells in a cascading structure. These cells are called fast binary-to-decimal (FBD) and low-area binary-to-decimal (LABD) converters. In this paper, we show that despite the fact that their architectural framework for digit-by-digit decimal multiplication and the proposed hybrid multi-operand binary-to-decimal converter are correct, some logical equations presented for FBD converter cell are incorrect. Moreover, there exist ambiguities in presenting the logical equations of both FBD and LABD converter cells. Thus, we represent the correct and optimized equations for FBD and LABD converter cells using truth tables.