Combined technique for capacitance and slow trapping characterization of narrow bandgap MIS structures

Abstract

Slow trapping of carriers in the interface and in the insulator of MIS devices can add, depending on their magnitude, an important component to measured low and high frequency C- V characteristics. Standard capacitance characterization methods, in general, neglect slow trapping both in the measurement and in the analysis procedures. This may lead to ambiguous and incomplete results when applied to hysteretic MIS devices. In the present paper we describe a novel technique, which combines high and low frequency capacitance measurements with slow trapping measurements. This technique is based on the charge-capacitance ( Q- C) setup but includes a special analog locking circuit, enabling separation and quantitative measurement of slow trap charge as a function of gate voltage. The information obtained enables correction of the capacitance characteristics by subtracting slow trapping contributions. The corrected curves are “hysteresis free” and thus unambiguous analysis of surface potential, bulk doping and fast states density can follow. The features of the combined system are demonstrated by measuring the hysteretic InSb-anodic oxide interface. A logarithmic dependence between slow trapping and surface carrier concentration is experimentally found in the above interface. This dependence is consistent with a direct tunneling injection mechanism of free carriers into insulator traps.