Combined Effects of Guard Rings and Buried n<sup>+</sup> Layer on Mitigating Charge Collection and Charge Sharing in 90 nm CMOS Process

Abstract

A model of combining of guard rings and buried n+ layer in mitigating charge collection and charge sharing is presented in this paper. 3-D TCAD simulation results indicate that for 90-nm CMOS process, PMOS charge collection and charge sharing can be mitigated more effectively with the combination model than the solely use of guard rings or buried n+ layer. With the combination, a noticeable improvement on angled ion strikes is also represented. The model shows a significant advantage in high-energy ion strikes and angled ion strikes.