Abstract
This paper presents a method for multilevel logic optimization for combinational and synchronous sequential circuits. The circuits are optimized through iterative addition and removal of redundancies. Adding redundant wires to a circuit may cause one or many existing irredundant wires and/or gates to become redundant. If the amount of added redundancies is less than the amount of created redundancies, the transformation of adding followed by removing redundancies will result in a smaller circuit. Based upon the Automatic Test Pattern Generation (ATPG) techniques, the proposed method can efficiently identify those wires for addition that would create more redundancies elsewhere in the network. Experiments on ISCAS-85 combinational benchmark circuits show that best results are obtained for most of them. For sequential circuits, experimental results on MCNC FSM benchmarks and ISCAS-89 sequential benchmark circuits show that a significant amount of area reduction can be achieved beyond combinational optimization and sequential redundancy removal.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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