Abstract

The capabilities of plasma doping (PLAD) associated with flash lamp annealing have been evaluated to meet the ITRS requirements for 45nm CMOS node. First, material studies of P+/N junction fabricated by PLAD and activated by flash were performed via Secondary Ion Mass Spectrometry (SIMS) and Transmission Electron Microscopy (TEM) analysis. The results were then compared with the standard annealing approach via Rapid Thermal Annealing (RTP) using Ultra Low Energy (ULE) implantations and PLAD. For the first time, P+/N and N+/P PLAD junctions activated by flash annealing were electrically measured on specific structures in order to extract junction current leakage. Finally, the sheet resistance and junction depth trade-off of such fabricated USJ fulfils the 45nm ITRS specifications with acceptable junction leakage current.

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