Abstract
The capabilities of plasma doping (PLAD) and flash lamp annealing (FLA) for use in ultra-shallow junction (USJ) fabrication have been evaluated. Silicon wafers have been doped in a BF 3 plasma using wafer biases ranging from 0.6 to 1 kV and a dose of 4 × 10 15 cm −2. The wafers so implanted have been heat-treated by FLA using pre-heating temperatures in the range of 500–700 °C, peak temperatures of 1100–1350 °C, and effective anneal times of 20 and 3 ms. Secondary ion mass spectrometry (SIMS) and sheet resistance measurements have been undertaken to determine the junction depth and the sheet resistance, respectively. Optimum processing conditions have been identified under which both high electrical activation and insignificant dopant diffusion occur compared to the as-implanted state. In this way, one can obtain combinations of junction depth and sheet resistance that meet the 45 nm technology node requirements.
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