Column selection solutions for L 1 data caches implemented using eight‐transistor cells

Abstract

Voltage scaling can reduce power dissipation significantly. SRAM cells (which are traditionally implemented by using six-transistor cells) can limit voltage scaling because of stability concerns. Eight-transistor (8T) cells were proposed to enhance cell stability under voltage scaling. 8T cells, however, suffer from costly write operations caused by the column selection issue. A proposed technique, Read-Modify-Write (RMW), addresses this issue at the expense of extra read operations. The extra cache access affects performance and power dissipation negatively. In this study, the authors show that a large share of the cache accesses in RMW is unnecessary. To address this inefficiency, they propose two micro-architectural solutions with the aim of reducing the overhead imposed by RMW. The authors first proposed technique, Write Grouping (WG), relies on a buffering mechanism that identifies the redundant and the unnecessary cache accesses imposed by RMW and eliminates them. Their second technique, WG and Read Bypassing (WG + RB), improves the WG's efficiency further at a negligible area cost. Their simulation results show that on average, WG and WG + RB reduce RMW's cache traffic overhead by 15% and 20%, respectively. They show that WG and WG + RB also improve average performance by 30% and 37%, respectively.