Collector junction modeling of planar transistors

Abstract

This work obtains a correlation between the physical structure and capacitance characteristics of collector junctions of planar bipolar epitaxial transistors. It uses an exponential model to represent the impurity distribution and makes available by non-destructive techniques base impurity profile constant, background concentration and collector junction depth from terminal measurements. The methods take care of such aspects of device geometry which are particular to small area high frequency transistors. Procedures are proposed for systematic evaluation of stray and sidewall capacitances. The latter can be used to monitor junction depth. Of interest for quick estimation of parameters is a method that utilises derivatives of the C( V) plot and does not require evaluation of strays.