CoGNN: An Algorithm-Hardware Co-Design Approach to Accelerate GNN Inference With Minibatch Sampling

Abstract

As a new algorithm of graph embedding, Graph Neural Networks (GNNs) have been widely used in many fields. However, GNN computing has the characteristics of both sparse graph processing and dense neural network, which make it difficult to be deployed efficiently on the existing graph processing accelerators or neural network accelerators. Recently, some GNN accelerators have been proposed, but the following challenges have not been fully solved: 1) The mini-batch GNN inference scenario has the potential of software and hardware co-design, which can bring 30% computation amount reduction, and this is not well utilized. Besides, the cost of Message Flow Graph construction is large and may account for more than 50% of the total delay. 2) The feature aggregation has a large amount of data access and relatively small amount of computation, which leads to low on-chip data reuse, only 10% of dense computing. 3) Without the optimization of sparse computing units, simple memory bank and cross bar architecture can easily lead to bank access conflict and load imbalance, reducing the utilization of computing units to less than 60%. In order to solve the above problems, we propose a algorithm-hardware co-design scheme to accelerate GNN inference, which includes three technologies: 1) A reuse-aware sampling method is proposed for mini-batch inference scenarios, which reduces 30% of the calculation and improves the on-chip reusability of local data. 2) Through the node-wise parallelism-aware quantization, the features and weights are quantized to integers with eight or four bits, which reduces the amount of memory access by at least four times. 3) An accelerator supporting the above technologies is designed and evaluated, and different operations are supported by the sampling-inference integration architecture. The multi-bank on-chip memory pool is designed to support data reuse, and edge stream reordering is used to reduce data access conflicts, improving the utilization of computing units by 1.5x. Combined with the above technologies, the experiments show that our design achieves 9.2× speedup and 29× energy efficiency improvement compared with Deep Graph Library framework running on servers equiped with CPU and GPU.