Code generation for distributed embedded systems with VDM-RT

Abstract

Developing embedded systems that are distributed is a challenging endeavour, since they need to ensure system-wide properties as well as existence of a large number of possible candidate system architectures. Various model based techniques advocate raising the abstraction level in order to support a holistic view of such a distributed embedded system. Furthermore, automatically generating implementation specific code from models can support realisation efforts including avoiding inconsistencies between model and code. In this paper we present how such efforts can be aided for a distributed embedded system modelled in the real time dialect of the Vienna Development Method, VDM-RT, by means of automatic code generation. The contributions in this paper are (1) code generation capabilities for distributed embedded system modelled in VDM-RT; (2) demonstration of its applicability for an industrial case study involving a distributed interlocking system from the railways domain. Additionally, we discuss the balance between code generation for a model, which assumes idealised communication (no messages lost), and manually produced code, e.g. in the industrial case study legacy low-level code ensures fault-tolerant communication in the final implementation.