CNTFET-Based Ternary Logic Gates

Abstract

In the recent digital designs, there are certain circumstances where energy efficiency and ease is required, and in such situations, ternary logic (or three-valued logic) is favored. Ternary logic is an auspicious supernumerary to the conventional binary (0, 1) logic design techniques as this one is possible to attain straightforwardness and energy efficiency. This chapter deals with the comparative analysis of CMOS and CNTFET-based ternary inverter and universal gates design. The simulation result is analyzed and validated with a Hailey simulation program with integrated circuit (HSPICE) simulations. The average delay and power consumption in CNTFET-based ternary inverter have been reduced by approximately 90.3% and 48.8% respectively, as compared to CMOS-based ternary inverter design. Likewise, delay is reduced by 50% and power gets 99% reduction in ternary CNTFET NAND gate as compared to CMOS-based ternary NAND gat. It is concluded that CNFETs are faster and consume less power compared to CMOS technology.