CNTFET based 2-bit Unary weighted Current Steering Digital to Analog Converter using Cascode Current Mirror Technique

Abstract

In this work, we present the design and analysis of a 2-bit Current Steering (CS) Digital to Analog Converter (DAC) of Unary weighted architecture with 1GHz clock frequency. The proposed CSDAC architecture is designed in a 32nm technology node using a Carbon nanotube FET device; with 0.9V supply voltage and is based on Cascode current Mirror technique. The simulation study has revealed that the unique properties of CNTs and the high output impedance of the Cascode Current mirror technique have made the proposed CSDAC significantly stabilize the output current and reduces the glitches. The static performance parameter like INL & DNL, for the proposed CSDAC, have decreased by 81.5% & 32% respectively and dynamic performance parameter like SFDR has increased by 64 % in comparison to the Simple Current Mirror Unary weighted CSDAC(SM_CSDAC). The power consumption for the proposed CSDAC has got decreased by ~13% in comparison to the NMOS-based CSDAC. The performance parameters like Differential nonlinearity (DNL), Integral nonlinearity (INL), and SFDR of the proposed CSDAC have improved by 10%, 93 %, and 25% compared with the NMOS-based CSDAC using Cascode current mirror technique. The glitch energy of the proposed CNTFET CSDAC is 79% less than that of CMOS CSDAC, thus improving the working accuracy.