Abstract
Current steering Digital to Analog Converter (DAC) is architecture with advantages of high conversion rate, linearity and constant output impedance. A Segmented current steering DAC to improve dynamic performance is presented in this paper. To demonstrate the technique, 8 bit CMOS DAC is designed and layout is prepared in 90 nm technology. Computation of Integral Non Linearity (INL) and Differential Non Linearity (DNL) performance parameters is done. Chip consumes 57 mW and core area of 5483 (µm)2.
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