Abstract
3D integration utilizing TSV (Through-Silicon Via) is a promising technology to achieve high performance 3DIC (three-dimentional integrated circuit), not only because it exponentially increases connection efficiency between dies, but also because it can be practically integrated into current IC manufacture processes with minimal impact on both FEOL and BEOL design and processing. During construction of TSV, CMP (Chemical-Mechanical Polishing) is required to reveal the vias and finish the wafer surface for future processing. Reported in this paper is our recent effort in developing a series of slurries for TSV front-side polishing by close collaboration in device design, slurry formulation and process fine-tuning. Specifically, high through-put and well performed Cu slurries, along with high SiO2/Si3N4 selectivity barrier slurries, are introduced. These slurries are tested on laboratory-scale instruments as well as foundry CMP tools. Polishing results from both blanket and pattern wafers are discussed.
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