Abstract
A novel CMP-less planarization technology featuring a SOG/LTO (Spin-on Glass /Low-Temperature Oxide) etchback method is presented to develop a high-performance, low-cost, high-k/metal gate-last (HK/MG-last) integration process. For a special PMD (Pre-Metal Dielectric) poly-open-planarization, a new recessed three-step RIE (Reactive-Ion Etching) etchback process is developed in one process chamber. This method may replace general CMP with certain slurry. An etch-parameter study shows that an increase in the reaction gas pressure changes the SOG etch profile from convex to concave. This profile is more useful for realizing pseudo-global planarization of the entire PMD structure. The within-the-wafer PMD thickness uniformity reaches 95%, 5 mm from the wafer edge. By controlling the etch-rate difference between the SOG and LTO, a micro-concave effect on a dummy gate is demonstrated and used as a better selective wet-etching dummy poly-Si gate in TMAH (Tetramethylammonium hydroxide). With this method, the HK/MG-last PMOSFETs exhibit good electrical characteristics as well as a similar variation trend to the planarization results.
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