CMOS-based piezo-FET stress sensors in Wheatstone bridge configuration

Abstract

This paper reports on the design and characterization of field effect transistor (FET)-based stress sensors (piezo-FETs). Each sensor is formed by four FETs connected as a Wheatstone bridge with a common gate electrode and merged source/drain diffusions. The sensors are operated in strong inversion and saturation and provide a differential voltage signal proportional to mechanical stress. Maximal stress sensitivities are achieved by using NMOS devices for σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x'y'</sub> and PMOS devices for (σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x'x'</sub> - σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y'y'</sub> ) and by their optimal orientations with respect to the crystallographic axes. Three designs optimized for low intrinsic offset (design A), low power consumption (design B) and small size (design C) are presented. The sensors were fabricated in a commercial 0.35 μm CMOS technology. Their sensitivities were characterized by application of well-defined normal and shear stress on a four-point bending bridge and a torsional bridge, respectively. Statistically meaningful values of the common-mode and intrinsic offset voltage variations were obtained from 95 samples on a wafer prober setup. Absolute sensitivities of ≈1 mV/MPa are reported for both sensors of design A with standard deviations of all offset voltages below 3 mV.