CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents

Abstract

Testing CMOS circuits for faults which cannot safely be detected by static test patterns has been a matter of intense research for years. Recently methods based on delay fault models have been developed for a safe detection of dynamic faults. At the same time, test methods based on overcurrent effects have found new interest due to the application of built-in current monitoring elements. This paper analyses some typical types of defects in CMOS circuits for their detectability either by delay effects or overcurrents. Advances and limitations of both basic approaches are discussed.