CMOS shallow-trench-isolation to 50-nm channel widths

Abstract

The applicability of shallow-trench-isolation (STI) for CMOS to 50-nm channel widths has been explored. Transistors with channel width to 50 nm and trench width to 200 nm have been fabricated. A comparison of several oxide-filled and polysilicon field-plate-filled STI structures is presented including processing, device performance, and isolation leakage. It is shown that V/sub th/ roll off as a function of channel width can be made as small as 65 mV and 145 mV at 100 nm channel width for polysilicon and oxide filled STI, respectively. Off-state currents less than 5/spl times/10/sup -12/ A//spl mu/m and subthreshold slope around 80 mV/dec have been reached. Isolation breakdown voltages are about 8 V. Poly-filled STI effectively reduces channel edge effects, and provides excellent off-state, on-state, and turn-on characteristics all the way to 50-nm channel widths.