CMOS Scaling Beyond 22 nm Node

Abstract

Silicon CMOS scaling continues to defy all previous doom and gloom scenarios and is poised to extend to 15 nm node. There is a paradigm shift though; in previous generations of CMOS (before 90 nm) both performance and transistor density scaling could be achieved simultaneously with passive cooling. Currently, the density scaling appears to continue unabated due to advances in optical lithography (immersion, phase contrast imaging, double exposure, etc). However, performance scaling requires power-performance trade off consideration as the peak performance is limited by heat dissipation that can be managed via passive cooling (< 100 watts/cm2). Nevertheless, performance targets for CMOS products are being met at system level by multi-core architecture which allows massive parallel data processing. Current and future CMOS scaling is undoubtedly being driven by innovations at all levels, including system architecture, circuit design, integration, device design and new high mobility channel materials. This presentation is focused on the channel materials which we believe are most promising for future CMOS nodes.