CMOS Junctionless Field-Effect Transistors Manufacturing Cost Evaluation

Abstract

Junctionless field-effect transistors (JL-FETs) contain no doping gradients, so they are thought to be simpler to process and less costly to manufacture than fin field-effect transistors (FinFETs). To check this assertion, process flows for CMOS JL-FETs on 300 mm SOI and bulk silicon substrates with 22 nm gate length are developed, and the manufacturing costs are calculated using a cost-of-ownership based approach. It has been determined that for a given substrate, the cost of the given JL-FET process flows is comparable with FinFET processing with less than 2% cost difference, while JL-FET processing on SOI costs are greater than 10% on bulk silicon. The largest component of process cost is due to photolithography.