CMOS four-quadrant multiplier using triode transistors based on regulated cascode structure

Abstract

A new CMOS four-quadrant multiplier consisting of two MOS transistors operated in the triode region with regulated cascode structures is introduced. This circuit employs the essential property that MOS transistors are bi-directional (or symmetric) devices. Simulation results show that for supply voltages of ±3 V, this circuit has <1% linearity error for a differential input range up to ±1.8 V. Total harmonic distortion (THD) with a 1.8 V (peak) input signal at either input terminal with a ±1.8 V DC voltage at the other terminal is less than 1%. The simulated –3 dB bandwidth of this multiplier is ~17 MHz.