CMOS DSB Transmitter With Low TX Noise for UHF RFID Reader System-on-Chip

Abstract

This paper presents a new design for a CMOS double-sideband (DSB) RF transmitter (TX) integrated circuit (IC) for UHF RF indentification (RFID) reader system-on-chip. Due to the strong demand for high linearity, low TX noise, and low cost, a CMOS passive up-conversion mixer with an adaptive bias circuit is proposed. High linearity of the passive mixer can be maintained over a wide range of dc levels from the dc-coupled IF signals using the proposed adaptive biasing circuit. A linear two-stage CMOS power amplifier (PA) follows the up-conversion mixer so that the overall third-order output intercept point (OIP3) of the two-stage PA is improved by the optimized design of the first stage in its biasing condition, the cell size, and due to inter-stage matching. The designed TX IC is fabricated using a 0.18-μm standard CMOS process and the implemented passive mixer exhibits a low double-sideband noise figure (DSB NF) of 4 dB and a high OIP3 of 13.3 dBm. The implemented PA exhibits a high-output 1-dB compression point (OP1dB) of 18 dBm, and a clear sweet spot in OIP3 of as high as 36.8 dBm at the two-tone average output power of 10 dBm. The implemented overall TX IC has a size of 960 × 670 × μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the overall circuit performed with a gain of 17.8 dB, a high OP1dB of 17.6 dBm, an OIP3 of 28 dBm, and has a low DSB NF of 11.2 dB while consuming a biasing current of 58 mA from a 3.3-V supply. The proposed design also satisfies the spectral mask of the RFID standard for an output power of up to 18 dBm for the double-sideband amplitude shift-keying signals.