CMOS based quadruple valued flip-flops

Abstract

The conventional binary logic consists of only two states-‘true’ and ‘false’, but in multi-valued logic (MVL) system a number of intermediate states between the true and false can be designed. Hence, the multi-valued logic enables more information to be handled in a much compact manner, especially suitable for handling big data. In quadruple valued logic (QVL) system the additional two intermediate states are designed as ‘partially known’ and ‘partially unknown’ which can be explored significantly to sequential logics also e.g. flip-flops, etc. With the demand of time the memory-levels can also be increased to a higher extend simply by applying MVL logics. The present paper deals with the design and simulation of different kind of flip-flops in QVL as a part of MVL system using CMOS.