Abstract
A hardware implementation of a real-time compressed-domain image acquisition system is demonstrated. The system performs front-end computational imaging, whereby the inner product between an image and an arbitrarily-specified mask is implemented in silicon. The acquisition system is based on an intelligent readout integrated circuit (iROIC) that is capable of providing independent bias voltages to individual detectors, which enables implementation of spatial multiplication with any prescribed mask through a bias-controlled response-modulation mechanism. The modulated pixels are summed up in the image grabber to generate the compressed samples, namely aperture-coded coefficients, of an image. A rigorous bias-selection algorithm is presented to the readout circuit, which exploits the bias-dependent nature of the imager's responsivity. Proven functionality of the hardware in transform coding compressed image acquisition, silicon-level compressive sampling, in pixel nonuniformity correction and hardware-level implementation of region-based enhancement is demonstrated.
Highlights
Dramatic advances in the field of computational and medical imaging over the past decades have enabled many critical applications such as night vision, medical diagnosis, quality control, and remote sensing applications [1,2,3,4,5]
For a typical image sensor, imaging involves reading out the values sampled at different pixels [21]; whereas in the case of compressed-domain hardware, a set of gain matrices is loaded to the pixel array, and the image sensor’s output would be a linear combination of the projection of the object’s reflectance function to the gain matrices [16,22]
The photodetector samples the integrated light coming from the sample, which is modulated by using the digital micromirror (DMM)
Summary
Dramatic advances in the field of computational and medical imaging over the past decades have enabled many critical applications such as night vision, medical diagnosis, quality control, and remote sensing applications [1,2,3,4,5]. The increasing demand in image quality and its fidelity needs an increase in pixel count and a sophisticated post-processing mechanism to efficiently store, transmit, and analyze this huge data [6,7,8,9]. Post-processing imposes extra latency and requires additive power consumption, which is troublesome for many low-power, real-time applications, and portable devices [17]. In the pursuit of seeking an efficient computational imaging hardware, which tends to address the memory efficiency, low power consumption and minimal latency requirements, we demonstrate a CMOS-based imaging hardware [19], which supports compression at the acquisition time [20], inside the pixel. Different applications, including nonuniformity correction and compressive sensing are discussed in Sections 6 and 7, and the experimental results are presented.
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