Close form delay model for on chip signalling with resistive load termination using: Current mode technique

Abstract

In this paper the closed form expression of delay model based on effective lump element resistance & capacitance, approximated distributed RC lines are presented with resistive load termination. The inductive effect is dominant at lower technology node is modelled using characteristic impedance of transmission line. First order transfer function is designed by applying the boundary condition at the source and load termination. And the dominant pole is calculated which determines the system response and delay of proposed model. A step response for restive load termination is developed. And it is accurately modelled for use in current mode signalling. For smaller value of load resistance, the peak value on line is decreased and due to it system performance gets improved in terms speed and average power consumption. From the mathematical analysis it has been analytically evaluated that current mode signalling is 2.77 times better than voltage mode.