Clock-Latency-Aware Pre-CTS for better Timing Closure in VLSI Design

Abstract

A common strategy for reducing the time jump due to a clock tree insertion is to add a clock uncertainty value. If a small clock uncertainty value is selected for the Pre-CTS optimization, then a significant timing jump is observed when the clock tree is inserted, and clock timings are propagated. On the other hand, if the clock uncertainty is large, then the place and route (PNR) flow does not converge. This approach has been proven to be insufficient as each timing path is affected differently by the creation of the clock tree. In this paper, we suggest a more targeted approach whereby all pins in the clock tree will be annotated with their estimated latency, and therefore clock arrival times under ideal clocks should closely model the post-CTS arrival times. This objective is achieved by introducing an accurate and fast clock prediction early in the flow at the pre-CTS stage. As a result, the transition from the pre-CTS stage to the post-CTS stage becomes easier without significant timing jumps. An experiment on nine commercial test cases led to a significant TNS timing improvement of up to 68%, with an average of 35% at the end of the route stage. The full PNR flow runtime is not impacted. We achieved a 3% average runtime reduction over all test cases. Keywords—Clock-latency estimation, Clock-tree Synthesis, Integrated circuit conception, Physical implementation, Static timing analysis, Static timing closure.