Abstract
A clocked hysteresis control scheme with power-law frequency scaling is proposed to improve the conversion efficiency at a light load current, and it is applied to a buck converter design. By replacing a continuously on comparator used in conventional hysteresis control by a clocked comparator with power-law frequency scaling, the buck converter consumes no direct current (dc) in the comparators. Almost flat efficiency over a load current ranging from 500 nA to 20 mA is achieved. In addition, a quick wakeup feature is maintained because of the inherent hysteresis control. As for the theoretical aspect, expressions for the frequency stability condition, power consumption, and output voltage ripple of the proposed power-law frequency scaling scheme are derived and analyzed. A leakage-based digitally controlled oscillator, which consumes only 3.5 nW when the frequency is 15 Hz for 500-nA load current, is designed to provide a clock signal to the clocked comparator. Experimental results show that the buck converter implemented with the power-law frequency scaling scheme achieves a 90.4% peak efficiency and higher than 87% efficiency over a load current range from 500 nA to 20 mA.
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