Clock rescheduling for timing engineering change orders

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With increasing circuit complexities, design bugs are commonly found in late design stages, and thus engineering change orders (ECOs) have become an indispensable process in modern VLSI design. Most prior approaches to the timing ECO problem are concerned about combinational logic optimization. In contrast, this paper addresses the problem in the sequential domain to explore more optimization flexibility. We propose an orthogonal method of post-mask clock scheduling with spare cells. Compared to traditional clock scheduling, clock scheduling in the ECO stage is more challenging in that it confronts limited spare-cell resources and dynamic changes of wiring cost incurred by different spare-cell selections. Based on mixed-integer linear programming (MILP), our formulation considers not only gate sizing and buffer insertion using spare cells, but also wire snaking. Experimental results based on five industrial designs show the effectiveness of our work. Our framework has been integrated into a commercial design flow.