Clock and Data Recovery IC for 40Gb/s FiberOptic Receiver

Abstract

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gbls. We report a 40-Gb/s CDR fabricated in indium-phosphide heteroJunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in tum, reduces the circuit complexity (transistor count) and the vollage-eontrolled oscillator (YCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an extemal demultiplexer, and low-frequency PLL control loop and on-chip Umiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.