Cleanliness testing for process acceptability

Abstract

The art of characterizing chemical residues on a printed circuit board following assembly, and testing the impact of those residues on electrical performance, is neither trivial nor an easy exercise. Residues that may not affect one component type may have significant implications for other component types. The acceptability of the residue condition on a PCB design needs to be tested at the point of the manufacturing process, just before conformal coating. Reliability labs perform surface insulation resistance (SIR) electrical testing on industry standard or custom designed test boards. SIR is a useful process control method for measuring the activity level of ions trapped in the pad area and under the body of leadless components. Electrical performance testing confirms reliability at environmental conditions that the assembly experiences during its useful life. SIR is the preferred method for providing objective evidence that the process conditions used to assemble the boards meet manufacturing standards for the finished product. The purpose of this research is to validate an SIR fully integrated test instrument that was designed for cleanliness testing to achieve process acceptability at the manufacturing site. Component-specific test boards assembled with solder pastes that meet J-STD-004 classifications of ROL0, ROH0, REM0, REH0 and ORL1, followed by cleanliness testing for process acceptability using SIR testing, IPC TM650-2.6.3.7 method will be performed. The test boards will undergo three cleaning conditions of no-cleaning, partial cleaning and complete cleaning. Data findings, inferences from the data findings and conclusions will be presented.