Circuit Techniques for Leakage Reduction

Abstract

This chapter proposes different integrated circuit techniques to reduce overall leakage in both logic and cache memories. The subthreshold or weak inversion conduction current between source and drain in a metal–oxide semiconductor (MOS) transistor occurs when gate voltage. The leakage reduction techniques described in the latter sections utilizes these parameters in a MOS fluid–effect transistor to achieve a low leakage state. The gate direct tunneling current is due to the tunneling of electron from the bulk silicon through the gate oxide potential barrier into the gate. The different circuit techniques have been proposed to reduce leakage energy utilizing this slack without impacting performance. The low–power benefits without compromising performance, two methods of lowering supply voltage can be employed: static and dynamic supply scaling. The leakage currents in n-type MOS or p-type MOS transistors depend exponentially on the voltage at the four terminals of transistor. The access transistors benefit from the leakage reduction, the overall leakage savings is moderate.