Abstract
In this work, when dealing with transmission-gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay, power, and area minimization is worthwhile to improve the performance in high-speed designs[1]. In particular, by splitting such FFs into two sections that are separately optimized and then reconciling the results, the emerging design always outperforms the one resulting from the employment of a classical Logical Effort procedure assuming such FFs as a whole continuous path[1]. Simulations have been performed at transistor level on several well-known TGMS FFs, designed in 65-nm and 90nm technologies using Microwind3.1 CAD tool, and the results have been compared to validate the correctness of such a procedure and of the underlying assumptions. Significant improvements have been found on delay, power and on area occupation, thus showing that this approach allows correctly dealing with the actual path in such circuits and hence to more properly steering the design towards the achievement of efficiency in the high-speed region[1]. epaE� n � �� RGMCET, Nandyal,maheswari.mmr@gmail.comÂ
Highlights
Flip-Flops (FFs) are the basic building blocks of data path structures
Together with the circuits devoted to the clock generation and distribution, FFs are part of the clock network, which is responsible for 30%–50% of the whole chip energy budget .Latches and flip-flops are basic sequential elements commonly used to store logic values and are always associated with the use of clocks and clocking networks
SIMULATION RESULTS: The comparison table for before and after splitting the design examples in 90nm & 65nm technology have been presented
Summary
They allow for the storage of data processed by combinational circuits and the synchronization of operations at a given clock frequency [1] Due to their multistage structure, high clock switching activity, and increasing portion of clock period occupied by their timing latency, the speed and energy of FFs significantly affect the overall performance of a data path [2], [3]. Optimal FF design strategies are usually based on automated algorithms embedded directly into simulators [1], [3], [4] These algorithms are powerful methods to optimize constraints such as speed, energy consumption, or energy-delay products, even for complicated FFs consisting of several internal nodes. Large number of Master-Slave flip-flops and DET topologies having less power dissipation, delay and energy in 65nm and 90nm CMOS technology have been proposed
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