Circuit Cost Reduction for Online STDP using NIPIN Selector as Timekeeping Device in RRAM Synapse

Abstract

On-chip implementation of spike-time dependent plasticity in spiking neural networks using RRAM synapses requires pulse shaping circuits (PSC) to drive RRAMs. PSCs convert the temporal separation between pre and post neuron spikes to appropriate voltages that get applied across the synapse. The speculation of PSCs consuming the majority of circuit resources in the neuron circuits calls for methods simplifying the PSC. A recently demonstrated NIPIN timekeeping device based selector facilitates this, showing learning with square pulses using its inherent hole storage physics. However, a quantitative advantage achieved by utilizing a timekeeping device to evaluate its necessity is unavailable in the literature. Also, a model is required to carry out large scale circuit simulations for crossbar arrays using this device as selector. In this work, we design and compare the PSCs for different selector devices proposed in the literature to show 133× reduction in energy per spike and 8× reduction in the area of neuron circuit using NIPIN as the selector device compared to previously shown diode selector. We also present an experimentally calibrated model for the device for future explorations. Our results show that the small fraction energy and area occupied by the leaky-integrate and fire part of the circuit makes optimization of PSCs a priority. Thus, our work highlights the importance of mimicking biology by the use of simple spikes from neurons and performing time-keeping at the synapse in implementations of learning circuits.