Circuit analysis and optimization by partial matrix elimination with a new strategy of variable time step

Abstract

In this paper a fast algorithm of partial matrix elimination (PME) combined with a new strategy of variable time step (VTS) is developed for transient analysis of nonlinear circuits containing interconnects. In PME the admittance matrix in the MNA equation of circuit analysis is arranged to consist of two submatrices. The lower submatrix, which contains contributions of only linear elements, is constant for a fixed time step and is partially triangulated by Gauss elimination for several time step values picked out by the new VTS strategy. At each Newton iteration, Gauss elimination is needed only for the upper submatrix, which contains contributions of nonlinear devices. PME with the new strategy of VTS is faster and more accurate than traditional Gauss elimination (TGE) with VTS for circuit analysis. Moreover, the efficiency of circuit optimization can be improved with PME.