Abstract
Actually, SoC design is based on the reuse of Intellectual Property (IP). Designer's attempts such as flexibility, cost constraints, high performance and time to market can thus be helpfully managed. However, the correct integration of the generated architectures/components in a design implies complex verification and design problems. Since IPs are heterogeneous, the design of communication interfaces between them is more and more difficult. In this paper, we present a CIG: Communication Interface Generator; a CAD tool automating the integration process of hardware accelerators/ coprocessors aiming data flow emerged systems.
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