Effective IP reuse for high quality SOC design

Abstract

Intellectual property (IP) reuse is essential for meeting the challenges of system-on-a-chip (SoC) design productivity improvement, design quality and meeting time-to-market goals. However, IP quality issues in terms of inadequate test coverage, low power capability, absence of functional features etc. has led to reduced benefits from reuse. This is because the IP is usually designed for use in one chip and later on (re)used in chips having different requirements. Hence, part of SoC design productivity is spent in enhancing the IP to the desired quality level. In a joint development program with the customer, where it is required to integrate some of their IPs, the usual paradigm followed for reuse has to be enhanced beyond the state-of-the-art to meet the design goals. As updated versions of the IP may be released several times during the SoC design phase, managing the design database poses challenge with respect to the IP enhancements.