ChipsetT: Embedded Die Substrate Applications

Abstract

Embedded die substrate technologies are being developed in an assortment of configurations and for different market segments. The technology being discussed in this paper will be focused on both a fan out technology – ChipsetT Fan-Out and a system in package approach (ChipsetT SiP) in which a multiple component bill of materials (BOM) is used. The Chipset process is based on the WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multilayer polyimide flex wiring and conductive z-axis sintered metal interconnections. This ChipsetT Fan Out technology allows for large scale production of fan out type solutions which can allow for very thin packages in addition to unique pin out solutions such as pin compatibility for a competitor part. The ChipsetT SiP also allows embedding of single or multiple silicon die and/or components. Additional components can also be placed using conventional SMT on the top or bottom side of the package. There is a great deal of design flexibility with this technology which makes it a great solution for applications trying to reduce their x-y size or z-height. When utilizing RDL technology on the embedded die we are able to do the fine pitch routing in order to allow the substrate to route at larger pitches ensuring an overall cost effective solution. This paper will focus on the different classes of applications that have benefited from this technology and will discuss the benefits and tradeoffs of the different solutions that have been engineered. Assembly and reliability data will be presented on several of the applications showing a robust solution set.