Abstract
As a heterogeneous integration technology, the chiplet-based design technology integrates multiple heterogeneous dies of diverse functional circuit blocks into a single chip by using advanced packaging technology, which is a promising way to tackle the failure of Moore’s law and Dennard scaling. Currently, as process nodes move forward, dramatically rising cost, design cycle, and complexity are driving industry to focus on the chiplets. Chiplets allows IC designers to merge dies fabricated at different process nodes and reuse them in different projects, which helps to reduce the cost during design and improve yield. In this review, we look back at the industry’s efforts over the past decade and summary the concepts and techniques associated with chiplets. In the end, a discussion and conclusion will be given to forecast the future of chiplets.
Highlights
After decades of rapid development, large-scale integrated circuits have become the backbone of information technologies
Compared to XSR, USR SerDes mainly focuses on implementing high-speed interconnect communication of Die-to-Die at ultra-short distance (10 mm level) via 2.5D/3D packaging technology
It could guarantee the validity of its design and physical implementation, but the yield problem would still occur during the filtering and packaging process
Summary
After decades of rapid development, large-scale integrated circuits have become the backbone of information technologies. Industry and academia generally believe that the Post Moore’s Era [5] will come soon, which means longer-term research will focus on the More Moore technologies and efforts should be made in every aspect of semiconductor industry along with scaling process such as design, device architectures, package process, even new devices beyond-CMOS to sustain power, performance, area and cost (PPAC). Electronics 2020, 9, 670 single package for developing dedicated heterogeneous chips via internal interconnection technology This solution solves the problems of scale, development costs and period efficiently. In academia, University of California, Georgia Institute of Technology, and European research institutions [10,11] begin to research the chiplet-related problems, including the interconnect interfaces, packaging, and applications. We wish that our efforts could provide references for researchers engaged in the research and design of the next-generation chips
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