Charge Trapping Mechanisms in Nitridated SiO<sub>2</sub>/ 4H-SiC MOSFET Interfaces: Threshold Voltage Instability and Interface Chemistry

Abstract

Silicon dioxide (SiO2) layers deposited on 4H-SiC and subjected to different post deposition annealing (PDA) in NO and N2O were studied to identify the key factors influencing the channel mobility and threshold voltage stability in lateral implanted 4H-SiC MOSFETs. Cyclic gate bias stress measurements allowed to separate the contributions of interface states (Nit) and near interface oxide traps (NIOTs) in the two oxides. The reduction of these traps in the NO annealed sample is due to the lower amounts of sub-stoichiometric silicon oxide (~1nm) and carbon-related defects (<1nm) at the interface, as could be demonstrated by Electron Energy Loss Spectroscopy. The experimental results indicate that limiting the SiC re-oxidation during post-deposition annealing in MOSFET technology is a key factor to improve the mobility and threshold voltage stability.