Charge trap NAND technologies

Abstract

In the last years a big research effort has been spent in the study of new technologies that could represent a possible alternative to conventional floating gate (FG) NAND. In fact even if FG NAND is the dominant technology and there is no advice of reduction in scaling pace, several physical roadblocks seem to limit future scalability (e.g. electrostatic interference among adjacent cells). Charge trap (CT) memories may overcome some of these limitations and represent the best candidate to substitute FG devices for future nodes [1]. Differently from floating gate cells that have a semiconductor as storage element, in CT case electrons are trapped inside a dielectric layer. The different storage material change drastically cell architecture impacting also on physical mechanisms for write operations (both program and erase) and reliability.